1. Field of the Invention
The present invention relates to a circuit and method for providing a corrected duty cycle.
2. Description of the Related Art
Generally, a delay locked loop (DLL) is used in a synchronous semiconductor memory device, such as a double data rate synchronous dynamic random access memory (DDR SDRAM), to perform synchronization between an internal clock signal and an external clock signal of the synchronous semiconductor memory device. When the external clock signal is input to the synchronous semiconductor memory device, a time delay occurs due to a clock skew between the external clock signal and the internal clock signal. Therefore, the DLL is employed in the synchronous semiconductor memory device for generating the internal clock signal by compensating the clock skew.
The DDR SDRAM inputs and/or outputs data at rising and falling edges of the clock signal to increase the transmission speed of data. As the operational speed of the DDR SDRAM is increased, performance of the DDR SDRAM is greatly affected by performance of the DLL. In addition, variations in process, supply voltage and temperature can affect the driving ability of the circuit, thereby creating timing and/or noise problems and worsening the design margin of the duty cycle. Since reliable data transmission is achieved in DDR SDRAM when the duty cycle is equivalent to 50%, a duty cycle correction method applied to the DLL is required for ensuring sufficient design margin of the duty cycle.
FIG. 1 shows a digital duty cycle correction circuit 100 disclosed in U.S. Pat. No. 7,015,739. The digital duty cycle correction circuit 100 includes a duty cycle detector circuit 104 configured to receive a first internal clock signal ICLK and a second internal clock signal ICLKB. A comparator circuit 106 is configured to receive output signals of the duty cycle detector circuit 104 and provide a comparison result. A counter circuit 108 is configured to perform an addition and/or a subtraction operation according to the comparison result so as to provide digital codes, and a digital to analog converter (DAC) 110 is configured to generate control signals according to the digital codes. Based on the above, the digital duty cycle correction circuit 100 requires the counter circuit 108 to perform a duty cycle correction and requires the DAC 110 to convert the signals. Therefore, the circuit 100 is complex and requires a large silicon area.
Alternatively, an analog structure to simplify the duty cycle correction circuit is desirable. Such circuit needs a fast response for correcting the internal clock signal larger or smaller than a desired duty cycle to avoid external noise disturbance.